Finding Defects With E

Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips.

Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have their place. The new systems are faster and offer better resolution than the previous equipment, but they also are more expensive and have some throughput limitations.

For years, chipmakers have relied on e-beam and optical inspection systems in advanced logic and memory fabs. Those technologies are complementary. Optical-based systems are fast and they are used to inspect an entire wafer for defects, but resolution is limited. E-beam has better resolutions, but it’s slower.

In an e-beam inspection system, electrons are generated within the tool, which then hit the surface of a die. The electrons scatter and bounce back to a detector, enabling it to find defects in chips. Compared with optical, e-beam inspection has significantly higher sensitivities — somewhere in the 1nm range. But it could take hours, if not days, to inspect a full wafer.

Because of that, e-beam inspection is used only to examine a small part of a die for defects, usually when optical can’t find certain defects. Often this happens in R&D, where problematic defects need to be located and rooted out. Then, in the fab, chipmakers use optical inspection tools to monitor and find chip defects in production. E-beam inspection is also used in fabs for select applications.

Optical inspection will remain the workhorse tool in fabs. But e-beam also plays an important role, and possibly an expanding one. “E-beam inspection is needed when you require high sensitivity and you need to find those difficult defects,” said Risto Puhakka, president of VLSI Research. “Let’s say you have a defect. You can’t recognize it with optical in a normal monitoring line. E-beam has its place here. You can run wafers through the system and figure out what’s going on. You do the root cause and cost analysis and all of that.”

While e-beam inspection is slow, next-generation tools promise to speed up the process, whether using a single- or multi-beam approach. Both types claim to find defects that other systems can’t detect. “I’m sure they are faster than the previous generation tools,” Puhakka said. “You can have tricks to make it faster. But it’s still slow.”

So the new e-beam tools won’t replace optical. E-beam inspection is still used “where you need high sensitivity, but the downside is that you have to accept a productivity loss,” Puhakka said.

Equipment makers are trying to change that perception, as evidenced by the activity in this market:

Applied Materials, meanwhile, continues to offer its current single-beam e-beam inspection system.

Chip challenges Amid a downturn in the IC market last year, the e-beam inspection market fell from $370 million in 2018 to $235 million in 2019, according to VLSI Research. In 2020, the e-beam inspection market is expected to rebound and reach about $300 million, according to the firm.

The overall wafer inspection market, including e-beam, optical and review tools, was a $3.04 billion business in 2019, according to VLSI Research. Of that figure, the optical inspection market is 11 times larger than the e-beam segment.

In the fab, all chips require wafer inspection. Take logic for example. At 28nm and above, chips incorporate planar transistors with larger feature sizes. Using various wafer inspection systems, chipmakers have little or no difficulties finding defects in planar devices.

Chips based on planar transistors are still widely used today at 28nm and above, but they actually reached their physical limit at 20nm. So starting in 2011, chipmakers migrated to finFET transistors at 22nm and 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Fig. 1: FinFET vs. planar. Source: Lam Research

FinFETs provide more performance at lower power than planar transistors, but they are more expensive and harder to make in the fab. Consequently, process R&D and design costs have skyrocketed. Now, the cadence for a fully scaled node has extended from 18 to 30 months.

Today, leading-edge chipmakers are ramping up 7nm and 5nm finFET processes, with 3nm in R&D. The challenges are escalating at each node. The devices are becoming more complex with smaller feature sizes.

In a 28nm planar device, for example, a transistor may have a 117nm to 120nm contacted gate pitch (CPP) and a 90nm metal pitch, according to WikiChip, a technology site. In comparison, TSMC’s new 5nm finFET process features a 48nm CPP and a 30nm metal pitch, WikiChip reported. The CPP measures from one transistor’s gate contact to the gate contact on the adjacent device.

At 3nm and/or 2nm, chipmakers plan to migrate from finFETs to a gate-all-around transistor technology. One gate-all-around type, called nanosheet FETs, is a finFET on its side with a gate wrapped around it.

“For sure, 3nm will be more difficult than 5nm, which was more difficult than 7nm,” said Rick Gottscho, CTO of Lam Research. “There is a lot more complexity in a nanowire or nanosheet than in a finFET. There are new processes, and those are very challenging.”

Fig. 2: FinFET vs. nanosheet. Source: Imec

Nanosheets provide some price/performance benefits over finFETs, but there is only an incremental reduction in scaling. “The move from finFET to nanosheet is redefining the new era of how an increase in computer power and higher transistor densities will be achieved. It will be about changing the transistor architecture rather than making things smaller,” said Douglas Guerrero, senior technologist at Brewer Science.

The challenges aren’t limited to logic. “Whether it’s 3D NAND, DRAM or logic, everything is shrinking in the lateral direction in ‘x’ and ‘y,’ and then increasing in the ‘z’ direction. Everything is getting taller, deeper and smaller. Then, you have high-aspect ratio structures and very small regions where you have defects, and very small-size defects,” said Mohan Iyer, head of the E-beam Products Group at KLA.

That’s where wafer inspection fits in. These systems can find the problematic defects in chips. If the defects aren’t found, a chip may end up with poor yields or failures in the field.

Inspection flow To capture the defects, chipmakers use e-beam and optical inspection tools. Both systems are used to find physical defects, such as voids, protrusions, and bridges in chips.

E-beam leverages the properties of electrons, while optical uses photons. Basically, an optical inspection system uses a broadband light source to illuminate a wafer. Then, the light is collected and an image is digitized, which helps find defects on the wafer.

In the fab, chipmakers use inspection systems for engineering analysis, critical line monitoring, and line monitoring.

E-beam inspection is used for engineering analysis in the R&D group. E-beam is used to find tiny and problematic defects during the early stages of chip development. Once those defects are rooted out and the chip meets spec, the device line moves to the fab.

Critical line monitoring is conducted in the fab. The goal is to find the most critical physical defects in patterned wafers. Line monitoring, which is also done in the fab, also detects defects in wafers. Both monitoring processes mainly use optical inspection. E-beam tools are also used sometimes.

“There’s a place for both,” KLA’s Iyer said. “It comes down to sensitivity to detect and being able to visualize and see those defects. That’s on one side. On the other side there are other factors like coverage, speed and throughput.”

Indeed, there are several tradeoffs. Optical inspection is fast, but it also has a physical limit. Optical has sensitivities down to